EDN

Mentor provides concurrent HDL checking for FPGA and ASIC designers

Mentor Graphics released a new concurrent design checking and creation environment for FPGA and ASIC design teams working with Verilog, SystemVerilog, and VHDL design languages. The capability is ...
EDN

05.21.98 Optimize ASIC test suites using code-coverage analysis

Optimize ASIC test suites using code-coverage analysisMartin Abrahams, TransEDA Ltd, and Stuart Riches, Texas Instruments LtdPerforming code-coverage analysis of HDL code before synthesis saves time ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Fifteen years ago verification of FPGA designs was easy but as the size of FPGAs has increased so have the verification challenges, Jerry Kaczynski explains. Today it is not unusual for FPGA users to ...
Business Wire

Sigasi Transforms Design Development with Visual Studio Code Extension

GENTBRUGGE, Belgium--(BUSINESS WIRE)--Sigasi, the leading developer of hardware description language (HDL) design solutions, today announced the availability of its Visual Studio Code (VS Code) ...