Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
EDN

Mentor improves HDL suite for ASIC, FPGA designs

SAN MATEO, Calif.—Mentor Graphics Corp. has enhanced its HDL Designer Series front-end design suite to provide better ways to create and manage hardware description languages in ASIC and FPGA designs.
TechRepublic

FPGA Implementation of Interrupt Controller (8259) by Using Verilog HDL

A priority interrupt controller is a hardware designed chip which acts as an overall system manager to efficiently handle the multiple interrupts that tend to occur from the varied number of ...
WatersTechnology

Impulse Announces C-to-HDL FPGA Compiler

Impulse Accelerated Technologies has announced the latest version of its C-to-HDL compiler, providing field-programmable gate array (FPGA) coding support for Arista Switch users. FPGAs, which are ...
Design-Reuse

QuickLogic Announces Partnership with Aldec for eFPGA Simulation Flow

Sunnyvale, CA – February 20, 2018 – QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, display bridge and programmable logic ...