IEEE

Power Optimization Techniques During Synthesis and Physical Design for a Low-Power RISC-V Design

Abstract: With the proliferation of battery-operated systems, reducing power consumption in integrated circuits is increasingly critical. This paper introduces a comprehensive approach to reducing ...
GitHub

SGDH-RVSoC Project, a portable and Linux capable RISC-V computer system on an FPGA

The RVSoC Project was the origin, serving as a research and development project of the RISC-V computer system targeting FPGAs in Verilog HDL at Arch Lab, Tokyo Tech. Building on this foundation, we ...
CNX Software

Linux 6.18 LTS release – Main changes, Arm, RISC-V, and MIPS architectures

Linus Torvalds has just announced the release of Linux 6.18 on the Linux Kernel Mailing List (LKML), which will likely become the next LTS kernel [update: it’s now official]: So I’ll have to admit ...
IEEE

Architectural Exploration and Performance Enhancement of the CVA6 RISC-V Core Using the Gem5 Simulation Framework

Abstract: As embedded devices continue to proliferate in applications ranging from IoT to edge computing, optimizing SoC architectures like CVA6 for performance and efficiency has become increasingly ...