IEEE

Design of a Hybrid Branch Prediction Architecture for Risc-V Processors

Abstract: Branch prediction is critical for performance in modern high-speed processors, whereas branch prediction error results in pipeline flush and execution ...
IEEE

Power Optimization Techniques During Synthesis and Physical Design for a Low-Power RISC-V Design

Abstract: With the proliferation of battery-operated systems, reducing power consumption in integrated circuits is increasingly critical. This paper introduces a comprehensive approach to reducing ...
GitHub

SGDH-RVSoC Project, a portable and Linux capable RISC-V computer system on an FPGA

The RVSoC Project was the origin, serving as a research and development project of the RISC-V computer system targeting FPGAs in Verilog HDL at Arch Lab, Tokyo Tech. Building on this foundation, we ...