IEEE

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

Abstract: This paper presents a 40-Gb/s/pin single-ended PAM-4 transceiver for GDDR7. LV-POD interface that separates the internal voltage from the channel supply voltage (VDDQL) is used to reduce ...
IEEE

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

Abstract: A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design ...